This disclosure relates to a method for manufacturing a semiconductor structure. This disclosure further relates to a semiconductor structure, and an electronic device.
Silicon is the basic material for present solid-state electronics, and processing techniques have been evolved for decennials. Hence, most electronic integrated circuit devices are based on silicon. However, the relatively low charge carrier mobility and its indirect band gap are disadvantages and limit the use of silicon in particular in opto-electronic applications. It would be advantageous to combine more suitable semiconductor materials, such as II-VI, III-V or IV-IV compound semiconductors with silicon-based electronics on common silicon substrates.
A monolithic integration of compound semiconductors on silicon wafers is desirable and has extensively been in the past. Several problems need to be overcome when compound semiconductors and conventional silicon technologies are be combined. First, there is a large lattice mismatch between a crystalline silicon substrate and compound semiconductor crystals. Further, there is a thermal expansion coefficient mismatch between the (silicon) wafer material and the active compound semiconductor material. Additionally, a structural mismatch between the diamond crystal structure of Si and the polar crystal structures of III-V and II-VI compound semiconductors may occur. It is an overall goal to achieve high crystalline quality over various monolithic layers for compound semiconductor on a foreign substrate such as silicon.
In an effort to achieve high crystalline quality in crystalline material layers that show a lattice mismatch, several methods have been developed. For example, direct epitaxy of blanket layers allow for a gradual transition from one lattice parameter to the next. However, relatively thick transition layers are needed to reduce the defect density considerably.
Techniques to combine compound semiconductor materials with conventional silicon wafers include bonding techniques. In direct wafer bonding, a compound heterostructure is fabricated on a donor wafer wherein the donor wafer material is eliminated after bonding with the conventional silicon wafer. This makes the bonding technology relatively expensive. Further, bonding is limited to the size of costly compound substrate wafers.
Another approach for combining lattice-mismatched materials such as compound semiconductors with silicon substrates is the aspect ratio trapping approach. Aspect ratio trapping (ART) refers to a technique where crystalline defects are terminated at non-crystalline, for example dielectric, sidewalls. U.S. Pat. No. 8,173,551 B2 discloses a method where a silicon substrate is covered with a dielectric layer defining trenches through to the substrate material. In the trenches, epitaxial films of a compound material are deposited wherein particular geometries of the growth front are realized. The aspect ratio of the trenches needs to be large enough to terminate the defects that nucleate at the silicon-compound interface so that higher parts of the crystalline compound show a low crystalline defect density. Some approaches of the ART technique teach the use of germanium microcrystals grown in silicon oxide trenches on a silicon substrate with a gallium arsenide film on top.
Another approach is disclosed in “High-quality single-crystal Ge on insulator by liquid-phase epitaxy on Si substrates” by Y. Liu, M. D. Deal and J. D. Plummer, Appl. Phys. Lett. 84, 2563 (2004). Amorphous germanium is encapsulated by dielectric layers on top of a silicon substrate. After being melted by rapid heating, germanium recrystallizes during a cooling process. Crystalline defects originating from the seed window terminate at the dielectric walls due to the geometry of the encapsulated volume. Using this method, it is possible to obtain a semiconductor material free from crystalline defects, e.g. twinning defect. Also the recrystallization of the III-V semiconductors InAs and GaSb with this method was recently demonstrated, as presented in “Optimal Device Architecture and Hetero-Integration Scheme for III-V CMOS” by Z. Yuan, A. Kumar, C.-Y. Chen, A. Nainani, P. Griffin, A. Wang, W. Wang, M. H. Wong, R. Droopad, R. Contreras-Guerrero, P. Kirsch, R. Jammy, J. Plummer, K. C. Saraswat, Symp. VLSI Techn. Digest 2013. On the other hand, diffusion and intermixing effects of the semiconductor material occur due to the applied high temperature, and it is difficult to apply this technique for recrystallizing ternary compounds, e.g. indium gallium arsenide. Furthermore, it is not possible to obtain sharp hetero-junctions via this technique.
It is therefore desirable to provide improved devices comprising lattice mismatched crystalline semiconductor materials and methods for fabricating such.